Die
ASIC layout
V2PRO architecture
ANAKONDA (ZuSE-KI-AVF)
- Initial Tape-out
- 2025
Involved Chipdesign Germany Members
Description
Technical Specifications
- Die Area
- 9 mm²
- Interfaces
- SPI, UART, GPIO, AXI4 via STAB, 64bit parallel bus
Architecture Details
- ISA
- V2PRO
- Cores
- 4
- Clock Frequency
- 1500 MHz
Process & Development
- Foundry
- GlobalFoundries
Funding & Project Context
- Project
- ZuSE-KI-AVF
- Funder
- BMBF
- Grant ID
16ME0379- Runtime
- 2022-2025
Licenses
- IP Blocks (own)
- V2PRO coprocessor
- IP Blocks (3rd party)
- 16Gbit/s SerDes
EDA Tools Used
- Cadence Genus (Synthesis)
- Cadence Innovous (Place & Route)
Verification Methods
- Simulation
- FPGA-Prototyping (Zynq UltraScale+)
Project Partners
- Institute of Microelectronic Systems, Leibniz University Hannover
- Dream Chip Technologies GmbH
- Robert Bosch GmbH
- Cadence Design Systems GmbH
- Institute for Communication Technologies and Embedded Systems (RWTH Aachen)
- Division of Microelectronic Systems Design (RPTU)
- Chair for Chip Design for Embedded Computing (TU Braunschweig)
The information displayed on this page has been provided by the listed Chipdesign Germany members and has not been verified by Chipdesign Germany.












